| Rule Violations |
Count |
| Room 10 (Bounding Region = (212.675mm, 48.856mm, 225.807mm, 69.176mm) (InComponentClass('10')) |
0 |
| Room 9 (Bounding Region = (199.721mm, 48.856mm, 212.853mm, 69.176mm) (InComponentClass('9')) |
0 |
| Room 8 (Bounding Region = (186.767mm, 48.856mm, 199.899mm, 69.176mm) (InComponentClass('8')) |
0 |
| Room 7 (Bounding Region = (173.813mm, 48.856mm, 186.945mm, 69.176mm) (InComponentClass('7')) |
0 |
| Clearance Constraint (Gap=0.127mm) (All),(All) |
0 |
| Width Constraint (Min=0.2mm) (Max=0.508mm) (Preferred=0.254mm) (All) |
0 |
| Power Plane Connect Rule(Relief Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All) |
0 |
| Short-Circuit Constraint (Allowed=No) (All),(All) |
0 |
| Un-Routed Net Constraint ( (All) ) |
0 |
| Hole Size Constraint (Min=0.025mm) (Max=3.5mm) (All) |
0 |
| Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All) |
0 |
| Hole To Hole Clearance (Gap=0.254mm) (All),(All) |
0 |
| Minimum Solder Mask Sliver (Gap=0.254mm) (Disabled)(All),(All) |
0 |
| Silk To Solder Mask (Clearance=0.254mm) (Disabled)(IsPad),(All) |
0 |
| Silk to Silk (Clearance=0.254mm) (Disabled)(All),(All) |
0 |
| Net Antennae (Tolerance=0mm) (All) |
0 |
| Silk primitive without silk layer |
0 |
| Modified Polygon (Allow modified: No), (Allow shelved: No) |
0 |
| Room 3 (Bounding Region = (121.997mm, 48.856mm, 135.129mm, 69.176mm) (InComponentClass('3')) |
0 |
| Room 1 (Bounding Region = (96.089mm, 48.856mm, 109.221mm, 69.176mm) (InComponentClass('1')) |
0 |
| Room 2 (Bounding Region = (109.043mm, 48.856mm, 122.175mm, 69.176mm) (InComponentClass('2')) |
0 |
| Room 4 (Bounding Region = (134.951mm, 48.856mm, 148.083mm, 69.176mm) (InComponentClass('4')) |
0 |
| Room 5 (Bounding Region = (147.905mm, 48.856mm, 161.037mm, 69.176mm) (InComponentClass('5')) |
0 |
| Room 6 (Bounding Region = (160.859mm, 48.856mm, 173.991mm, 69.176mm) (InComponentClass('6')) |
0 |
| Total |
0 |
